The present invention pertains to a digital signal processor (hereafter called DSP) that is a processor specifically developed for high-speed digital signal processing of grouped digital signals, and in particular, it pertains to an improvement in DSP operation testing.
Conventional DSPs are explained below. In FIG. 3, symbol 101 is a conventional DSP. This DSP 101 has external input terminals 111-113, DSP circuit 102, interface circuit 103, and external output terminals 131-133. This DSP 101 is constituted so that when external input terminals 111-113 are connected to the output terminal of an external device, such as a digital modem, and external output terminals 131-133 are connected to the input terminal of an external device, signals output by an external device are input into interface circuit 103 and signals that are output from interface circuit 103 can be input into an external device via external output terminals 131-133. Note that in FIG. 3 only external input terminals 111-113 and external output terminals 131-133 are shown, but more external input terminals and external output terminals can be provided.
Interface circuit 103 is a circuit that converts input signals into a form that can be processed by DSP circuit 102. In normal operation, signals are input into DSP circuit 102 after conversion, and after arithmetic processing is performed by the DSP core 104 in DSP circuit 102, they are output to interface circuit 103.
Then interface circuit 103 converts the arithmetically processed results input from DSP circuit 102 and outputs them to an external device via external output terminals 131-133, and therefore the entire DSP 101 is able to control the external device.
As an example of a case where operation testing is performed before a DSP 101 such as this is installed, instead of an external device, a tester, which is not shown, is connected to external input terminals 111-113 and to external output terminals 131-133, specific signals are input from this ester to external input terminals 111-113, and signals output from external output terminals 131-133 are read by the tester. By determining if the output signals agree with predetermined specifications, it can be determined whether DSP 101 is operating correctly.
However, there are problems with the aforementioned operation testing of DSP 101. Specifically, signals are transmitted via interface circuit 103, so even if it is determined that the operation of DSP 101 is abnormal, it is impossible to determine whether this is due to a faulty DSP circuit 102 or due to a faulty interface circuit 103, and since DSP circuit 102 cannot be coupled directly to the tester, the operation of DSP circuit 102 alone cannot be tested.
So, self-testing, in which the DSP circuit 102 tests its own operation by producing test data inside the DSP circuit 102, bypassing interface circuit 103, has been proposed.
In order to execute this self-testing, data transfer circuit 105, memory 106, data hold circuit 107, and multiplexer 120 are provided for DSP circuit 102.
With self-testing, during test setup, test programs, and setting information required for test data production are written to memory 106 from DSP core 104. After this, when test execution has started, test programs, setting information, etc. are supplied to DSP core 104 from memory 106.
Next, test data and control instructions with the same specifications as data input to DSP core 104 during normal operation are produced by DSP core 104 based on the test programs and output to data transfer circuit 105. Test data and control instructions are output to multiplexer 120 from each data line L111 and L112 in data line group 140 from data transfer circuit 105.
Multiplexer 120, during actual operation, connects output signal line group 150 of interface circuit 103 to DSP core 104, but during test operations it connects data line group 140 to DSP core 104 based on control instructions output from DSP core 104. Consequently, the test data generated by data transfer circuit 105 are input to input terminals IN1 and IN2 of the DSP core.
Input test data are arithmetically processed by DSP core 104 and the results of the arithmetic processing are output to data line group 160 from output terminals T1 and T2. The arithmetic processing results output to data line group 160 are held by data hold circuit 107 and output in a specific order to input terminal TDI on DSP core 104. Finally the output is re-input to DSP core 104.
The arithmetic processing results input to input terminal TDI are compared with the correct arithmetic processing results already held in DSP core 104 and it is determined whether the arithmetic processing that was performed was correct or not. After this, new test data are produced by DSP core 104, and the sequence of arithmetic processing and evaluation processing discussed above is repeated the exact number of predetermined times. When all the executed arithmetic processing results equal the correct arithmetic processing results, the DSP circuit 102 is judged to be good by the DSP core 104 itself. Then, by outputting the results of this evaluation from data line Lr. to an external circuit, which is not shown, self-testing is completed.
In this way, self-testing has the advantage that the DSP circuit 102 can be tested while bypassing interface circuit 103, so it is possible to test only the DSP circuit 102, which would have been impossible with operation testing using a tester.
Also, there is a halt terminal HALT, which is an operation halt/continue control terminal for DSP core 104, in DSP core 104, and there is a test that determines whether the operation of DSP 101 can be halted normally by means of halt terminal HALT (hereafter called hold testing).
When hold testing is performed by self-testing, halt terminal HALT and data transfer circuit 105 are connected via multiplexer 120, DSP core 104 outputs a halt signal via data transfer circuit 105, and the halt signal is input to halt terminal HALT. When a stop signal is input to halt terminal HALT, the operation of DSP core 104 itself is halted. The result is that not only is it impossible for the DSP core 104 itself to determine whether the halt state is good, but processing cannot be restarted.
The present invention was created to solve problems such as these in the prior art. Its objective is to provide a digital signal processor DSP, which allows core self-testing, and after the core itself has been halted, it can be determined whether the core""s halt state is good by restarting the core.
In order to solve the aforementioned problems, the digital signal processor described therefor herein is constituted by having a processor for processing digital signals, a memory that holds data for self-testing of the aforementioned processor, a data transfer circuit into which are input self-test control data, which are output by the aforementioned processor for the processor and that supplies the relevant self-test control data to the aforementioned processor, an operation controller into which control signals are input from the aforementioned processor and that supplies operation control signals to the aforementioned processor after a specified time has elapsed, a first switching circuit that is installed between an external input terminal, the aforementioned data transfer circuit and a data input terminal of the aforementioned processor and that selects data supplied from either the aforementioned external input terminal or the aforementioned data transfer circuit and outputs the data to the aforementioned data input terminal, and a second switching circuit that is installed between the aforementioned input terminal, a halt terminal of the aforementioned processor, aforementioned data transfer circuit, and the aforementioned operation control circuit, and that selects one of the signals supplied from the aforementioned external input terminal, the aforementioned data transfer circuit, or the aforementioned operation control circuit and outputs the signal to the aforementioned halt terminal. When the aforementioned processor inputs signals, which indicate to halt the operation of the processor, to the aforementioned halt terminal via the aforementioned data transfer circuit and the aforementioned second switching circuit during self testing, the aforementioned operation control circuit outputs the aforementioned operation control signals to the aforementioned halt terminal via the aforementioned second switching circuit after a specified time has elapsed in response to the aforementioned control signals output from the aforementioned processor, and the aforementioned processor is returned to an operating state.
In addition, the digital signal processor is a digital signal processor described in claim 1, and therefor may have a data hold circuit that holds self-test result information based on the aforementioned self-testing control data output from the aforementioned processor.
Additionally, the digital signal processor of therefor may output digital signal processor described in claim 2, and the aforementioned processor outputs internal state information to the aforementioned data hold circuit describing the halt state during self-testing after operation restarts in response to the aforementioned operation control signals output from the aforementioned operation controller.
In addition, the digital signal processor described in claim 4 is a digital signal processor described in claim 2 or 3, where the aforementioned therefor may receive input of self-test result information output from the aforementioned data hold circuit and compares the self-test result information with expected test results and outputs the comparison results of the outside.
Additionally, the digital signal processor of is a digital signal processor described in claim 1, therefor may and has an interface circuit that serves as an interface between the aforementioned processor and the outside.
With the digital signal processor of the present invention, in the hold (halt operation) self-test, even when the operation of the core halts due to the output of a halt signal by the core (processor) to itself, the operation of the core can be restarted by subsequent input of operation control signals from the operation control circuit to the halt terminal. For this reason, unlike in the past, when it would not have been possible to confirm the core""s halt state because the core could not be restarted after being halted, it is now possible to implement a hold test that can determine a good or bad core halt state.
Note that, with the present invention, after core operation halts by the input of a halt operation signal from the core to the halt terminal, the time until operation control signals are output to the halt terminal can be adjusted based on data strings, etc. By this configuration, the core operation halt time can be adjusted, so it is possible to conduct core hold testing for various halt times.
In addition, with the present invention, self-test result signals that indicate the results of self-testing, are compared with self-test results of anticipated self-testing and the comparison results are output to the outside, so whether or not the core is good can be confirmed easily on the outside.